1. Technical Field
The present invention relates to non-volatile memory, and more specifically, to systems and methods for improving the performance of non-volatile memory operations performed in a storage subsystem.
2. Description of the Related Art
Non-volatile memory (NVM) manufacturers typically build in timing cycles to accommodate the time that is needed to complete page program and block erase operations. For flash memory, a typical page program cycle may last about 200-250 μs, with a maximum of 500-750 μs, and a typical block erase cycle may last about 1.5 ms, with a maximum of 2 ms. However, timing is not uniform across the physical NVM devices and the actual time it takes to complete a page program or block erase operation can vary. Therefore, in many systems, a controller that executes such an operation is required to constantly poll the status register in a programming loop until the operation is completed. The time spent in this waiting state is often wasted and system performance suffers as a result.